Various process technologies exist for producing dynamic random access memory (DRAM) devices. One fabrication scheme involves floating gates, where a given DRAM storage cell is formed from a silicon-on-insulator (SOI) transistor such that charge is stored in the body of the transistor, rather than in a trench or stack capacitor. The stored charge for a “floating body” DRAM creates a back-gate bias adjustment to the transistor threshold voltage.
Similar to a conventional trench or capacitive DRAM, access to a row of memory cells of a floating body DRAM (FBDRAM) is carried out via a row of sense amplifiers. However, the sense signal generated by a given FBRAM cell is significantly larger in magnitude than that of a trench or capacitor DRAM cell. As a result, FBDRAM sense amplifiers may be configured to operate at significantly lower power parameters.
While FBDRAMs have the ability of providing low-power advantages, signal attenuation associated with read operations may occur in certain circumstances.